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hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 1 - 1999 hyundai system ic div ision preliminary description hv71 3 1b is a highly integrated single chip cmos color image sensor using hyundai 0.5um cmos process developed for image application to realize high efficiency r/g/b photo sensor. the sensor has 648 x 488 pixel array , and in general color interpolation method using 3x3 spatial mask with window size 642 x 482 pixels may be used for vga(640x480) display mode . each compact active pixel element has high photo-sensitiv ity and converts photon energy to analog voltage signal. the sensor has three on-chip 8 bit digital to analog convert (dac) and 64 8 comparators to digitize the pixel output. the three on-chip 8 bit dac can be used for independent r/g/b gain control. hyundai proprietary on-chip correlated double sampling ( cds ) circuit can reduce fixed pattern noise (fpn) dramatically. the whole 8 bit digital color raw data is directly available on the package pins and just a few control signals are needed for whole chip control so that it is very eas y to configure cmos imaging system. features l 64 8 x 48 8 pixels resolution l full function control through standard i 2 c bus l active pixel size: 8um x 8um l built-in automatic gain control agc l high efficiency r/g/b color photo sensors l 48pin clcc / 20pin cdip l integrated 8-bit adc for direct digital output l bayer rgb color pattern l low power 3.3v operation (5v tolerant i/o) l anti-blooming circuit l integrated pan control and window sizing l flexible exposure time control l clock speed up to 15 mhz l integrated on-chip timing and drive control l programmable frame rate and synchronous format l 1/ 3 " optical format technical specification functional block diagram pixel resolution 64 8x 48 8 pixel size 8x8um 2 fill factor 30% format vga sensitivity 2. 2 v/luxsec supply voltage for analog 3.3v supply voltage for digital 3.3v supply voltage for 5v tolerant input 5.0v power consumption @15mhz operating temperature 0~40 centigrade technology 0.5um 3metal cmos pixel array adc block line buffer decoder/pixel driver i 2 c control register & logic
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 2 - 1999 hyundai system ic div ision preliminary electrical characteristic s absolute maximum ratings l supply voltage(analog, digital) : 3.0 v ~ 3.6 v l voltage on any input pins : 0 v ~ 5.0 v l operating temperature (centigrade) : 0 ~ 40 l storage temperature(centigrade) : -30 ~ 80 note : input pins are 5v tolerant. stresses exceeding the absolute maximum ratings may induce failure. dc operating conditions symbol parameter units min. max. load[ pf] notes v dd internal operation supply voltage volt 3.0 3.6 v ih input voltage logic "1" volt 2.0 5 6.5 v il input voltage logic "0" volt 0 0.8 6.5 v oh output voltage logic "1" volt 2.15 3.6 60 v ol output voltage logic "0" volt 0.4 0.4 60 t a ambient operating temperature celsius 0 40 ac operating conditions symbol parameter max operation frequency units notes mclk main clock frequency 15 mhz 1 sck i 2 c clock frequency 400 k hz 2 1. mclk can be divided according to clock divide register for internal clock. 2. sck is driven by host processor. for the detail serial bus timing, refer to i 2 c spec.
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 3 - 1999 hyundai system ic div ision preliminary electro-optical characteristics color temperature of light source: 3200k / ir cut-off filter ( cm-500s, 1mmt) is used. parameter units min. typical max. note sensitivity mv / lux ? sec 1600 2200 - 1) dark signal mv /sec - - 50 2) output saturation signal mv 1200 - - 3) dynamic range db - - 48 4) output signal shading % - 8 13 5) dark signal shading mv/sec - - 10 6) frame rate fps - - 45 7 ) note: 1) measured at 2 8 l ux illumination for exposure time 10 ms . 2) measured at zero illumination for exposure time 50 ms . ( t temp = 40 centigrade ) 3) measured at v dd =3.3v and 100lux illumination for exposure time 50msec. 4) 48db is limited by 8-bit adc . 5) varia nce of average value of 4x4 pixel s response of each block over all equal blacks at 50% saturation level illumination for exposure time 10msec. 6) range between v max and v min at zero illumination for exposure time 50msec, where v max and v min are the maximum and minimum values of each block ? s response, respectively. 7) measured at mclk 15mhz. integration time must be set in order for effective window height not to exceed window height. it ? s because effective window height is directly proportional to integration time.
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 4 - 1999 hyundai system ic div ision preliminary input / output ac characteristics l all output timing delays are measured with output load 60[ pf]. l output delay include the internal clock path delay[6ns] and output driving delay that changes in respect to the output load, the operating environment, and a board design. l due to the variable valid time delay of the output, output signals may be latched in the negative edge of mclk for the stable data transfer between the image sensor and a host for less than 15mhz operation. mclk to hsync/vsync timing t 1 : mclk rising to hsync/vsync v alid maximum time : 18ns [output load: 60pf] t 2 : hsync/vsync v alid time : minimum 1 c lock(subject to t 1 , t 2 timing rule) mclk to data timing t 3 : mclk rising to data valid maximum time : 18ns [output load: 60pf] note ) hsync signal is high when valid data is on the data bus. mclk hsync/vsync t 2 t 1 t 1 t 3 data[7:0] valid data mclk t 3
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 5 - 1999 hyundai system ic div ision preliminary input / output ac characteristics (continue) enb timing t 4 : enb setup time : 5 [ ns ] t 5 : enb hold time : 5 [ ns ] t 6 : enb valid time : minimum 2 clock reset timing must in valid(active low ) state at least 8 mclk periods mclk t 5 t 4 enb t t 6
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 6 - 1999 hyundai system ic div ision preliminary input / output ac characteristics ( c ontinue) i 2 c bus (programming serial bus) timing i 2 c bus interface timing parameter symbol min. max. unit sck clock frequency f sck 0 400 khz time that i 2 c bus must be free before a new transmission can start t buf 1.2 - us hold time for a start t hd ;s ta 1.0 - us low period of sck t low 1.2 - us high period of sck t high 1.0 - us setup time for start t su ;s ta 1.2 - us data hold time t hd ;d at 1.3 - us data setup time t su ;d at 250 - ns rise time of both sda and sck t r - 250 ns fall time of both sda and sck t f - 300 ns setup time for stop t su ;s to 1.2 - us capacitive load of each bus lines(sda,sck) c b - - pf sda sck stop start tbuf tlow tr thd;sta thd;dat thigh tsu;dat tsu;sta tsu;sto stop start tf thd;sta
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 7 - 1999 hyundai system ic div ision preliminary pin configuration (48 pin clcc) pin9~16, pin19~20, pin33~ 41 : no connection color pattern pin no. name pin no. name 1 sck 26 dgnd 2 dgnd 27 data3 3 enb 28 data2 4 dgnd 29 data1 5 mclk 30 data0 6 vdd5 31 dvdd 7 avdd 32 dgnd 8 agnd 42 dvdd 17 agnd 43 reset 18 avdd 44 vsync 21 dgnd 45 hsync 22 data7 46 dgnd 23 data6 47 sda 24 data5 48 dgnd 25 data4 origin (0,0) (647, 487) die pixel array 1 0 646 487 486 read out start point 647 r g g b r g g b
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 1991011r_ 1.0 - 8 - 1999 hyundai system ic div ision preliminary pin configuration (20 pin cdip) color pattern pin no. name pin no. name 1 agnd 11 dvdd 2 data 7 12 reset 3 data 6 13 vsync 4 data 5 14 hsync/dvalid 5 data 4 15 sda 6 data 3 16 sck 7 data 2 17 enb 8 data 1 18 mclk 9 data 0 19 +5v tolerant bias 10 dgnd 20 avdd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (647, 487) die origin (0,0) active sensing area 487 486 647 646 1 0 r g g b r g g b read out star t point
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 9 - 1999 hyundai system ic div ision preliminary pin description (48 pin clcc) pin name i/o description 1 sck i i 2 c c lock ; i 2 c clock control from i 2 c master 2 dgnd i digital ground 3 enb i sensor enable signal ; 'h' enable normal operation 'l' disable 4 dgnd i digital ground 5 mclk i master clock (up to 15 mhz) ; global master clock for image sensor internal timing control 6 vdd5 i i/o bias voltage for 5v tolerant *1) 7 avdd i analog supply voltage 3.3v 8 agnd i analog ground 9 ~ 16 n.c no connection 17 agnd i analog ground 18 avdd i analog supply voltage 3.3v 19, 20 reserved reserved 21 dgnd i digital ground 22 data7 o image data bit 7 23 data6 o image data bit 6 24 data5 o image data bit 5 25 data4 o image data bit 4 26 dgnd i digital ground 27 data3 o image data bit 3 28 data2 o image data bit 2 29 data1 o image data bit 1 30 data0 o image data bit 0 31 dvdd i digital supply voltage 3.3v 32 dgnd i digital ground 33 ~ 41 n.c no connection 42 dvdd i digital supply voltage 3.3v 43 reset i hardware reset signal, active low 44 vsync o vertical synchronization signal / frame start output ; signal pulse at start of image data frame with programmable blanking duration 45 hsync /dvalid o horizontal synchronization signal / data valid output ; data valid when 'h' with programmable blanking duration 46 dgnd i digital ground 47 sda i/o i 2 c data ; i 2 c standard data i/o port 48 dgnd i digital ground *1) tie to dvdd for 3.3v operation / tie to 5v for 5v tolerant operation
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 10 - 1999 hyundai system ic div ision preliminary pin description (20 pin cdip) pin name i/o description 1 agnd i analog ground 2 data 7 o image data bit 7 ( msb ) 3 data 6 o image data bit 6 4 data 5 o image data bit 5 5 data 4 o image data bit 4 6 data 3 o image data bit 3 7 data 2 o image data bit 2 8 data 1 o image data bit 1 9 data 0 o image data bit 0 ( lsb ) 10 dgnd i digital ground 11 dvdd i digital supply voltage, 3.3v 12 reset i hardware reset signal, active low 13 vsync o vertical synchronization signal / frame start output ; signal pulse at start of image data frame with programmable blanking duration 14 hsync / dvalid o horizontal synchronization signal / data valid output ; data valid when 'h' with programmable blanking duration 15 sda i/o i 2 c data ; i 2 c standard data i/o port 16 sck i i 2 c clock ; i 2 c clock control from i 2 c master 17 enb i sensor enable signal ; 'h' enable normal operation 'l' disable sensor by stalling internal clock 18 mclk i master clock(up to 15mhz) ; global master clock for image sensor internal timing control 19 + 5 v i i/o bias voltage for 5v tolerant *1) 20 avdd i analog supply voltage 3.3v *1) tie to dvdd for 3.3v operation / tie to 5v for 5v tolerant operation
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 11 - 1999 hyundai system ic div ision preliminary register description mode_ a[8 ? h00] represent device identity. high nibble: sensor array size, low nibble: revision number for HV7131B, identity value is 8 ? h00, [vga: 0, revision 0] mode_ b[8 ? h01] this is operating mode select register. each bit's description is as below. bit function description 0 integration time unit selects integration time unit between line unit and pixel unit. commonly line unit is used for its large step control , but under high luminance or when precise control is needed in the case such as anti-flicker , pixel unit control is used . default is line unit mode [0]. 1 single frame mode selects continuous frame output and single frame output. when single shot mode is selected, only one frame data is produced and the sensor goes to idle mode. default is continuous frame output mode [0]. 2 window mode selects imaging array size between programmable window size and full size [648x488]. default is window size mode[1] and current window default size is 641x482. [window size is determined by rowstartaddress, column startaddress, windowwidth, windowheight registers.] 3 hsync output mode selects hsync output mode between ? data valid mode ? and ? data valid with clock mode ? . default is data valid mode[0]. 4,5 output data type selects output data type among ( data ? reference ) , data only or reference only . internally the sensor produces reference data and image data respectively , and image data is deducted by reference data in order to reduce fixed pattern noise. generally the technique is called correlated double sampling( cds) . default is data - reference ( cds) [00]. 6,7 operation mode selects sensor operation mode among normal sensing mode and chip test related modes. in normal use, the mode should be set to normal mode[00]. default is normal operation mode[00].
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 12 - 1999 hyundai system ic div ision preliminary mode_ c [8 ? h02] this is operating mode select register. each bit's description is as below bit function description 1 display mode selects color mode or black/white mode in black/white mode, gain control is controlled by g gain register value frame size control register s hv71 3 1b may image any user specif ied window area within image sensor array (648x488). this is called panning function , and for this function, frs(frame row start), fcs(frame column start), fwh(frame window height), and fww(frame window width) are used . panning window can be programmed as below. note1) metal shielded pixel element produce black level data, and effective image array size 646 x 486. in general, color interpolation algorithm using 3x3 spatial mask for mosaic cfa single sensor require that pixels around the edge of a programmed image window are used for just color interpolation of neighbor pixels. accounting for this fact, image array window should be programmed to larger value than the size that is to be displayed. for example, in order to make 64 0x 48 0 24bit color image data, 64 2x 48 2 pixel array is necessary. note2) you have to change the frame register value as below to get the full 64 0x 48 0 window size. { frsu, frsl } 3 { fwhu, fwhl } 482 { fcsu, fcsl } 3 { fwwu, fwwl } 642 (647,0) {fwhu, fwhl } (0,487) {fwwu, fwwl} {fcsu, fcsl} {frsu, frsl} metal shielding (1,1) (0,0) (646,486) (647,487)
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 13 - 1999 hyundai system ic div ision preliminary timing control register s l hsync b lank register [8 ? h20-8 ? h21] the hsync b lank register defines data blank time between current line and next line by pixel clock unit . the value programmed to hsync blank register defines hsync l ow time with (sensor array width ? window width) clocks added . for example, if window width = 500, hsync blank = 10, then hsync low time is hsync blank + (sensor array width ? window width), 10 + (648 ? 500) = 158 clocks. for more timing details, refer to frame timing diagram section. l vsync b lank register [8 ? h22-8 ? h23] the vsync b lank register defines the active high duration of vsync output by pixel clock unit . the active high vsync indicates frame boundary between continuous frames. for vsync-hsync timing relation in the frame transition, please refer to frame timing diagram section. l integration time value register [8 ? h25-8 ? h27] integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal adc processing. integration time is equivalent to exposure time in general camera so that integration time need to be increased in dark environment and decreased in light environment. integration time unit is selected between pixel unit and line unit by mode_ b[0 ] bit. when line unit mode is selected, only two lower bytes of integration time value register[8 ? h26-8 ? h27] are accounted in the internal sensor logic because representable maximum integration time, maximum value(2 16 -1) * sensor array width(648) * clock period(100ns for 10mhz) = 4.246 sec, is quite big enough to adapt to any very dark environment. for pixel unit mode, whole three bytes value are used for integration time, integration time value(8 ? h25-8 ? h27) * clock period, and representable maximum value is maximum value(2 24 -1) * clock period(100ns for 10mhz) = 1.677sec. sensor array width(648) window width(500) sensor array width(648) window width(500) hsync low time(158) hsync blank(10)
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 14 - 1999 hyundai system ic div ision preliminary l master clock divider register this four bits register is used to divide external pixel clock for internal use. the actual pixel operating frequency used in the sensor is the same as external pixel frequency divided by divisor as below. register value divisor register value divisor register value divisor 0 1 4 16 8 256 1 2 5 32 9 512 2 4 6 64 10 1024 3 8 7 128 11 2048 charateristics adjust ment register s each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrate internal sensing circuit in order to get optimal performance. there are three kinds of registers as below. l reset level register [8 ? h30] th e register controls the voltage level that is initially compared to pixel analog voltage , and the initial voltage level is called as ? reference voltage level ? . internal dac analog voltage decrements from reference voltage level until the pixel analog voltage output is lager than dac analog voltage. appropriate reference voltage level varies from various factors, such as process variation, luminance, etc. if the register value is set to too large or too small value , vertical fixed pattern noise may be produced. therefore this register value must be programmed to appropriate value in order to avoid fpn. for the automatic reset level control, please refer to reset level statistics register section. high register value means high reference voltage and large digital output. p rogram value range is 0~63, l rgb gain register s[8 ? h31-8 ? h33] there are three color gain registers for r, g, b pixels, respectively . th ese register s are used to amplify digital pixel output . if the gain register value is decreased, digital pixel output is increased. that is, under dark light condition the pixel output is not enough to get right image so that we must amplify the output value by decreasing gain value to get good image. these registers may be used for white balance and color effect with independent r ,g,b color control . p rogram value range is 0~63.
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 15 - 1999 hyundai system ic div ision preliminary l pixel bias voltage register [8 ? h34] the register controls pixel analog voltage decrement degree by controlling bias current of pixel output sensing load transistor. w ith the reset level register (8 ? h30) it is used to adjust adc circuit output characteristics . the larger register value causes the higher bias current to increase pixel output decrement degree, and commonly the register default value is used. program value range is 0~7. rset level statistics register l low reset level count[8 ? h57-8 ? h58] this two-byte register has a value representing a eighth (1/8) of pixels that have reset value less than 3 during one frame time and is updated when vsync gets active. with high reset level counter register it can be used as a parameter for external automatic reset level control logic that update the appropriate value in the reset level register to automatically compensate die to die overall reset level variation. l high reset level count[ 8 ? h59-8 ? h5a ] this two byte register has a value representing a eighth (1/8) of pixels that have reset value larger than 1 23 during one frame time and is updated when vsync gets active. with low reset level counter register it can be used as a parameter for external automatic reset level control logic that update the appropriate value in the reset level (30h) register to automatically compensate die to die overall reset level variation. rgb offset register s[8 ? h50-8 ? h52] these registers control offset value of rgb digital output to make color effect. normally these register values are set to default zero.
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 16 - 1999 hyundai system ic div ision preliminary register address and default value group symbol address description mode_a 00h device identity (read only : 00h ) operating mode selection ( default : 04h ) b0 0 line unit integration 1 pixel unit integration b1 0 continuous frame 1 single shot frame b2 0 full image (648x488) 1 windowed image b3 0 hsync only 1 hsync & internal clock b5 b4 output data type 0 0 data_level - reference_level 0 1 reference_level 1 0 data_level 1 1 reserved b7 b6 operating mode 0 0 normal mode 0 1 reserved 1 0 reserved 1 1 reserved mode_b 01h b1 0 color output 1 black & white output mode- registers mode_c 02h internal test register 53h, 55h, 56h, 60h, 61h [ reserved] test registers for image sensor future enhancement [these register should not be used in normal operation]
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 17 - 1999 hyundai system ic div ision preliminary register address and default value ( continue ) group symbol address description frsu 10h row start address (upper byte ) default : 00h frsl 11h row start address ( lower byte ) 0 3 h [ 3 ] fcsu 12h column start address ( upper byte ) 00h fcsl 13h column start address ( lower byte ) 0 3 h [ 3 ] fwhu 14h window height ( upper byte ) 0 1 h fwhl 15h window height ( lower byte ) e2 h [ 482 ] fwwu 16h window width ( upper byte ) 0 2 h frame- registers fwwl 17h window width ( lower byte ) 81 h [ 641 ] thbu 20h hsync blanking duration value ( upper byte ) default :00h thbl 21h hsync blanking duration value ( lower byte ) 03h tvbu 22h vsync blanking duration value ( upper byte ) 00h tvbl 23h vsync blanking duration value ( lower byte ) 03h titu 25h integration time value ( upper byte ) 00h titm 26h integration time value ( middle byte ) 01h titl 27h integration time value ( lower byte ) f4h timing- register tmcd 28h master clock divider 00h arlv 30h reset level value 38 h arcg 31h red color gain 1e h agcg 32h green color gain 1e h abcg 33h blue color gain 1e h adjust- register apbv 34h pixel bias voltage control 02h ofsr 50h r offset register 00h ofsg 51h g offset register 00h offset register ofsb 52h b offset register 00h lorefnoh 57h low reset level counter [<3] (upper byte) (read only) lorefnol 58h low reset level counter [<3] (lower byte) (read only) hirefnoh 59h high reset level counter [>1 23 ] (upper byte) (read only) reset level statistics register hirefnol 5 9 h high reset level counter [>1 23 ] (lower byte) (read only)
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 18 - 1999 hyundai system ic div ision preliminary programming sequence for cmos image sensor l single register byte programming s 22h a 01h a mode inform a p *1 *2 *3 *4 *5 *6 *7 *8 e set "operating mode" register into window mode *1. drive: i 2 c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 01h [sub-address] *5. read: acknowledge from sensor *6. drive: *7. read: acknowledge from sensor *8. drive: l multiple register byte programming using auto increment mode s 22h a 01h a 02h a 65h a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 e you can program multiple configuration registers with single i2c bus cycle. e set "row start address" register as 265h *1. drive: i 2 c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 10h [sub-address] *5. read: acknowledge from sensor *6. drive: 02h [row start address upper byte] *7. read: acknowledge from sensor *8. drive: 65h [row start address lower byte] *9. read: acknowledge from sensor *10. drive
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 19 - 1999 hyundai system ic div ision preliminary programming sequence for cmos image sensor ( continue ) l reading register value s 22h a 01h a s 23h a read data a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 e single read or auto-increment read e set "reset level value" register *1. drive: i 2 c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit(be careful. r/w=0)] *3. read: acknowledge from sensor *4. drive: 10h [sub-address] *5. read: acknowledge from sensor *6. drive: i 2 c start condition *7. drive: 23h(001_0001 + 1) [device address + r/w bit(be careful. r/w=1)] *8. read: acknowledge from sensor *9. read: read data from sensor *10. drive: acknowledge to sensor(if there is no more read data ack=1, else ack=0) *11. drive
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 20 - 1999 hyundai system ic div ision preliminary frame timing diagrams there are two frame timing cases, l integration time < effectivewindowheight * scale l integration time > effectivewindowheight * scale effectivewindowheight is equal to the number of data lines generated in a frame and is defined to be selected by if(( rowstartaddress + windowheight + 1) <= sensorarrayheight) effectivewindowheight = windowheight; else effectivewidnowheight = ( sensorarrayheight - rowstartaddress - 1); the above selection logic is somewhat confusing in respect of general counting measure. it ? s partly due to the mixed use of indexing start points, i.e. ? 0 ? and ? 1 ? in the chip design. therefore in order to avoid the confusion it is desirable to just follows the equation when you estimate the frame rate. for example, rowstartaddress = 200 and windowheight = 400, effectivewindowheight is 287 and 287 data lines per a frame are generated. scale is selected according to integration time mode by if( pixelmode) scale = sensorarraywidth; // for h7131b[648x488], sensorarraywidth is 648 else scale = 1; when integration time > ( effectivewindowheight * scale), next frame vsync does not follow immediately after current frame ? s last line has been produced. instead, one of the following two idle time slots is inserted according to integration time mode before next frame vsync gets active. sensorarrayheight [ 488 ] sensorarraywidth [ 648 ] rowstartaddress [200] windowheight [ 4 00] effectivewindowheight [ 287 ] (0,0)
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 21 - 1999 hyundai system ic div ision preliminary < idle slots > l line mode: (integration time - effectivewindowheight) * 1024 clks l pixel mode: (integration time - effectivewindowheigh t *scale) = (integration time - effectivewindowheigh t * sensorarraywidth) clks each frame timing of the above cases may be decomposed into four timing segments l initial data setup time after enb gets active l even line l odd line l frame transition the subsections will describe frame timing diagram for said frame time cases, (integration time < effective window height * scale) and (integration time > effective window height * scale) . 1. frame timing diagram for integration time < ( effectivewindowheight * scale) frame timing related registers are programmed to suit for the above condition as follows rowstartaddress = 3 ; windowheight = 482; columnstartaddress = 3 ; windowwidth = 642; integrationtime = 400 [line mode]; effectivewindowheight is ? 482 ? for ( sensorarrayheight > ( rowstartaddress + windowheight + 1)), i.e. 488 > (3 + 482 + 1), is met, and scale is ? 1 ? for integration time is line mode. therefore, (integration time < effectivewindowheight * scale), i.e. 400 < 482 * 1, is met. overall frames sequence initial data setup time line 0 line 1 , line 2 line 480 .... line 481 vsync line 0 line 1 , line 2 line 480 .... line 481 vsync line 0 line 1 , line 2 line 480 .... line 481 vsync .... frame 1 frame 2 frame 0
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 22 - 1999 hyundai system ic div ision preliminary mclk enb vsync delay slots fig. 1 initial data setup time after enb gets active mclk hsync data time slot clock ruler fig.2 even line data timing image raw data window width 642 clks r r enb deglitch 2 clocks sensor reset sensorarrayheight clocks [488 clocks] one line time delay ( sensorarraywidth + hblank) clocks [651 clocks] vsync 3 clocks integration time * scale clocks [400 * 648 clocks] line head blank 3 clks hblank 3 clks r g g r g r g r g line tail blank 3 clks sensorarraywidth (648) hblank(3) g
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 23 - 1999 hyundai system ic div ision preliminary mclk hsync data time slot clock ruler fig.3 odd line data timing mclk hsync vsync data time slot integration time < effectivewindowheight * scale fig.4 frame transition timing r g r . . . r . g g b . b . line head blank 3 clks line tail blank 3 clks image raw data window width 642 clks image raw data window width 642 clks hblank 3 clks g b g b g b g b g b line tail blank 3 clks line head blank 3 clks sensorarraywidth (648) hblank(3) g g b . g image raw data window width 642 clks vsync 3 clks ? ? hblank 3 clks
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 24 - 1999 hyundai system ic div ision preliminary 2. frame timing diagram for integration time > ( effectivewindowheight * scale) frame timing related registers are programmed to suit for the above condition as follows rowstartaddress = 3 ; windowheight = 482; columnstartaddress = 3 ; windowwidth = 642; integrationtime = 600 [line mode]; effectivewindowheight is ? 482 ? for ( sensorarrayheight > ( rowstartaddress + windowheight + 1)), i.e. 488 > (3 + 482 + 1), is met, and scale is ? 1 ? for integration time is line mode. therefore, (integration time < effectivewindowheight * scale), i.e. 600 > 482 * 1, is met, and idle slot of line mode, i.e. (600 - 482) * 1024 clocks idle slot, is inserted before the next frame initiation. overall frames sequence mclk enb vsync delay slots fig. 5 initial data setup time after enb gets active line 481 enb deglitch 2 clocks sensor reset sensorarrayheight clocks [488 clocks] one line time delay ( sensorarraywidth + hblank) clocks [651 clocks] vsync 3 clocks integration time * scale clocks [600 * 648 clocks] initial data setup time line 1 , line 2 line 480 .... line 481 line 0 line 1 , line 2 line 480 .... vsync line 0 line 1 , line 2 line 480 .... line 481 vsync idle time line 0 vsync idle time idle time frame 1 frame 2 frame 0
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 25 - 1999 hyundai system ic div ision preliminary mclk hsync data time slot clock ruler fig.6 even line data timing mclk hsync data time slot clock ruler fig.7 odd line data timing image raw data window width 642 clks r r line head blank 3 clks line head blank 3 clks image raw data window width 642 clks hblank 3 clks hblank 3 clks r g g b g g b r g g b r g g b r g g b line tail blank 3 clks line tail blank 3 clks sensorarraywidth (648) sensorarraywidth (648) hblank(3) hblank(3) g b g
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 26 - 1999 hyundai system ic div ision preliminary mclk hsync vsync data time slot integration time > effectivewindowheight * scale fig.8 frame transition timing r . . . r g g b g b . line tail blank image raw data window width line head blank . g image raw data window width vsync 3 clks ? ? idle slot (integration time - hblank 3 clks
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 27 - 1999 hyundai system ic div ision preliminary package dismension (48 pin clcc ) unit: mm * c : center of image area 0.5 3 0.15 0. 98 0.15 c
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 28 - 1999 hyundai system ic div ision preliminary package dimension (20 pin cdip ) unit: mm 0.5 3 0.15 0.98 0.15 1.27 +- 0.05 0.30 +- 0.10 2.60 +- 0.30 0.25 16.00 +- 0.12 12.00 +- 0.10 14.94 +- 0.11 15.24 +- 0.30 1.27 +- 0.25 5.00 0.46 +- 0.10 c
hv71 3 1b electronics industries co., ltd. cmos image sensor system ic div ision with 8-bit adc this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. da 3 199 1011 r_ 1.0 - 29 - 1999 hyundai system ic div ision preliminary memo hyundai electronics industries co., ltd system ic division headquarter & factory san 136-1,ami-ri ,bubal-eub,ichon-si,kyoungki-do,korea 467-860 tel : 82-336-630-2042/2484, fax : 82-336-639-1412, e-mail : wkkim@hei.co.kr

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